// 
// DSP project. (c) Copyright 2003 Wayne Wolf
// ALU module



`define PLUS 0
`define MINUS 1
`define AND 2
`define OR 3
`define NOT 4

module alu(fcode,op0,op1,result,oflo);
	parameter n=16, flen=3;
	input [flen-1:0] fcode; // operation code
	input [n-1:0] op0, op1; // operands
	output [n-1:0] result; // operation result
	output oflo; // overflow

assign
	{oflo,result} = 
		(fcode == `PLUS) ? (op0 + op1) :
		   (fcode == `MINUS) ? (op0 - op1) :
		      (fcode == `AND) ? (op0 & op1) :
			    (fcode == `OR) ? (op0 | op1) :
			       (fcode == `NOT) ? (~op0) : 0;
endmodule