module alu_testbench_v_tf();

// DATE:     16:03:04 12/17/2003 
// MODULE:   alu
// DESIGN:   alu
// FILENAME: testbench.v
// PROJECT:  alu
// VERSION:  


// Inputs
    reg [2:0] fcode;
    reg [15:0] op0;
    reg [15:0] op1;


// Outputs
    wire [15:0] result;
    wire oflo;


// Bidirs


// Instantiate the UUT
    alu uut (
        .fcode(fcode), 
        .op0(op0), 
        .op1(op1), 
        .result(result), 
        .oflo(oflo)
        );


// Initialize Inputs
    `ifdef auto_init

        initial begin
            fcode = 0;
            op0 = 0;
            op1 = 0;
        end

    `endif

	initial begin
	$monitor("op0 = %b, op1 = %b, fcode = %d, result = %b, oflo=%d\n",
				op0,op1,fcode,result,oflo);
     #20 op0 = 0; op1 = 1; fcode = 0;
	#20 fcode = 1;
	#20 fcode = 2;
	#20 fcode = 3;
	#20 fcode = 4;
     #20 op0 = 15; op1 = 0; fcode = 0;
	#20 fcode = 1;
	#20 fcode = 2;
	#20 fcode = 3;
	#20 fcode = 4;
     #20 op0 = 0; op1 = 15; fcode = 0;
	#20 fcode = 1;
	#20 fcode = 2;
	#20 fcode = 3;
	#20 fcode = 4;
     #20 op0 = 7; op1 = 8; fcode = 0;
	#20 fcode = 1;
	#20 fcode = 2;
	#20 fcode = 3;
	#20 fcode = 4;
     #20 op0 = 11; op1 = 11; fcode = 0;
	#20 fcode = 1;
	#20 fcode = 2;
	#20 fcode = 3;
	#20 fcode = 4;
	$finish;
	end

endmodule