module carryskip(a,b,carryin,sum,carryout);
	input [7:0] a, b; /* add these bits */
	input carryin; /* carry in*/
	output [7:0] sum; /* result */
	output carryout;
	wire [8:1] carry; /* transfers the carry between bits */
	wire [7:0] p; /* propagate for each bit */
	wire cs4; /* final carry for first group */

	fulladd_p a0(a[0],b[0],carryin,sum[0],carry[1],p[0]);
	fulladd_p a1(a[1],b[1],carry[1],sum[1],carry[2],p[1]);
	fulladd_p a2(a[2],b[2],carry[2],sum[2],carry[3],p[2]);
	fulladd_p a3(a[3],b[3],carry[3],sum[3],carry[4],p[3]);
	assign cs4 = carry[4] | (p[0] & p[1] & p[2] & p[3] & carryin);
	fulladd_p a4(a[4],b[4],cs4,     sum[4],carry[5],p[4]);
	fulladd_p a5(a[5],b[5],carry[5],sum[5],carry[6],p[5]);
	fulladd_p a6(a[6],b[6],carry[6],sum[6],carry[7],p[6]);
	fulladd_p a7(a[7],b[7],carry[7],sum[7],carry[8],p[7]);
	assign carryout = carry[8] | (p[4] & p[5] & p[6] & p[7] & cs4);
endmodule