module carry_lookahead_adder_testbench_v_tf();

// DATE:     17:22:23 12/16/2003 
// MODULE:   carry_lookahead_adder
// DESIGN:   carry_lookahead_adder
// FILENAME: testbench.v
// PROJECT:  cla
// VERSION:  


// Inputs
    reg [15:0] a;
    reg [15:0] b;
    reg carryin;


// Outputs
    wire [15:0] sum;
    wire carryout;


// Bidirs


// Instantiate the UUT
    carry_lookahead_adder uut (
        .a(a), 
        .b(b), 
        .carryin(carryin), 
        .sum(sum), 
        .carryout(carryout)
        );


// Initialize Inputs
    `ifdef auto_init

        initial begin
            a = 0;
            b = 0;
            carryin = 0;
        end

    `endif

	initial begin
	$monitor("a, b, c = %d, %d, %d  sum,carry = %d, %d\n",a,b,carryin,sum,carryout);
	#10 a = 0; b = 0; carryin = 0;
	#10 a = 0; b = 0; carryin = 1;
	#10 a = 0; b = 1; carryin = 0;
	#10 a = 0; b = 1; carryin = 1;
	#10 a = 1; b = 1; carryin = 1;
	#10 a = 2; b = 0; carryin = 0;
	#10 a = 1; b = 2; carryin = 1;
	#10 a = 3; b = 4; carryin = 0;
	#10 a = 15; b = 1; carryin = 0;
	#10 a = 1; b = 15; carryin = 0;
	#10 a = 8; b = 7; carryin = 1;
	#10 a = 33; b = 15; carryin = 0;
	#10 a = 127; b = 255; carryin = 0;
	#10 a = 1023; b = 32; carryin = 1;
	#10 a = 16'b1010101010101010; b = 16'b0101010101010101; carryin = 0;
	#10 a = 16'b1010101010101010; b = 16'b0101010101010101; carryin = 1;
	#10
	$finish;
	end


endmodule