// 
// DSP project. (c) Copyright 2003 Wayne Wolf
// ALU module



`define PLUS 0
`define MINUS 1
`define PLUS1 2
`define MINUS1 3
`define NEG 4

module alu(fcode,op0,op1,result,oflo,clk);
	parameter n=16, flen=3;
	input clk;
	input [flen-1:0] fcode; // operation code
	input [n-1:0] op0, op1; // operands
	output [n-1:0] result; // operation result
	output oflo; // overflow
        reg oflo;
	reg [n-1:0] result;

always @(fcode)
begin
	result = 16'bxxxxxxxxxxxxxxxx;
	oflo = 1'bx;
	
	case (fcode)
		`PLUS: begin {oflo, result} = op0 + op1; end
		`MINUS: begin {oflo, result} = op0 - op1; end
		`PLUS1: begin {oflo, result} = op0 + 1; end
		`MINUS1: begin {oflo, result} = op0 - 1; end
		`NEG: begin {oflo, result} = -op0; end
	endcase // case (fcode)
end
endmodule