// The complete DSP (without data or instruction memory).
// Written 14 April 2003 by Wayne Wolf. (c) Copyright 2003 Wayne Wolf.

module dsp(clk,rst,ival,iadres,dval,dadres,drw,regbval);

parameter n = 16; // instruction word width
parameter flen=3; // length of ALU opcode
parameter nreg=4; // number of registers

input clk, rst;
input [n-1:0] ival, dval; // value for instruction and data 
inout [n-1:0] iadres, dadres; // address for instruction and data
output drw; // read/write for data memory
output [n-1:0] regbval;

wire [nreg-1:0] rega, regb; // selected a, b registers
wire [n-1:0] regaval, regbval, regawrite; // data values from register file, data value to reg file
wire [flen-1:0] aluop;
wire regarw, regbrw;
wire overflow;

// synthesis attribute rloc of execute is X0Y0
ex execute(rst,clk,iadres,ival,dadres,dval,aluop,,overflow,rega,regb,regarw,regbrw,drw,regaval);
// synthesis attribute rloc of alu1 is X2Y2
alu alu1(aluop,regaval,regbval,regawrite,overflow,clk);
// synthesis attribute rloc of regfile is X0Y2
reg_file regfile(clk,regaval,rega,regarw,regawrite,regbval,regb,regbrw,dval);

endmodule