// 
// DSP project. (c) Copyright 2003 Wayne Wolf
// Execution module

module ex(rst,clk,iadres,inst,dadres,data,aluop,carryin,carryout,reg0,reg1,regarw,regbrw,drw,regaval);

	parameter n = 16; // instruction word width
	parameter nreg = 4; // number of bits in register field
	parameter nalu = 3; // width of alu opcode

	input clk, rst;
	input [n-1:0] inst,data,regaval;  // instruction and data from memory
	input carryout; // carryout from ALU
	output carryin; // carryin to ALU
	output [n-1:0] iadres; // address to memory
	output [n-1:0] dadres; // address to memory
	output [nalu-1:0] aluop; // opcode to ALU
	output [nreg-1:0] reg0, reg1; // addresses to register file
	output regarw, regbrw, drw; // read or write (same for both) 0 = read, 1 = write
	reg [n-1:0] ir; // instruction register
	reg [2:0] exstate; // state of the execution unit
        reg [n-1:0] iadres, dadres;
	reg regarw, regbrw, drw, carryin;
	reg [nreg-1:0] reg0;
	reg [nreg-1:0] reg1;
	reg [nalu-1:0] aluop;

// state codes for EX box
`define FETCH 0
`define DECODE 1
`define EXECUTE 2
`define LOADSTORE 3

// instruction format
// 15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0
// ADD,SUB       |  reg0         |  reg1         | xxxx
// LOAD,STORE    |  src/dest     |  address          
// JMP           |  PC offset
// JZ            |  reg          |  PC offset
//
// instruction fields
`define OPA n-1
`define OPZ n-4
`define ARG0A n-5
`define ARG0Z n-8
`define ARG1A n-9
`define ARG1Z n-12

// opcodes
`define ADD 0
`define SUB 1
`define LOAD 2
`define STORE 3
`define JMP 4
`define JZ 5
`define NOP 6

always @(posedge clk)// execute state machine
begin
    if(rst == 1) 
      begin
        exstate = `FETCH;
        regarw = 0;
        regbrw = 0;
        drw = 0;
        aluop = `NOP;
        iadres = 16'b0000000000000000;
      end
    else 
      begin 
		case (exstate)
			`FETCH : 
			    begin 
			        ir = inst; regarw = 0; regbrw = 0; drw = 0; exstate = `DECODE; aluop = `NOP;
			    end
			`DECODE : 
			    begin 
			        exstate = `EXECUTE; 
				if (ir[`OPA:`OPZ] == `JZ) // set up the test
					begin
					reg0 = ir[`ARG0A:`ARG0Z];
					end
				else if(ir[`OPA:`OPZ] == `JMP)
					begin 
					end
				else if (ir[`OPA:`OPZ] == `LOAD)
					begin
					// set up dest
					reg1 = ir[`ARG0A:`ARG0Z];
					// fetch me
					dadres = {8'b00000000, ir[`ARG1A:0]};	
					end

				else if (ir[`OPA:`OPZ] == `STORE)
					begin
					reg1 = ir[`ARG0A:`ARG0Z];
					// store to me
					dadres = {8'b00000000, ir[`ARG1A:0]};
					end
					
				else if (ir[`OPA:`OPZ] == `ADD)
					begin
					reg0 = ir[`ARG0A:`ARG0Z];
					reg1 = ir[`ARG1A:`ARG1Z];
					end
					
				else if (ir[`OPA:`OPZ] == `SUB)
					begin
					reg0 = ir[`ARG0A:`ARG0Z];
					reg1 = ir[`ARG1A:`ARG1Z];
					end
				end
				
			`EXECUTE :
			   begin
			        exstate = `LOADSTORE;
			        case (ir[`OPA:`OPZ]) // opcode
					`ADD : 
					begin //ADD
					iadres = iadres + 1;
					aluop = `ADD;
					carryin = 0;
					regarw = 1;
					end //ADD
					
					`SUB:
					begin
					iadres = iadres + 1;
					aluop = `SUB;
					carryin = 0;
					regarw = 1;
					end //SUB
					
					`LOAD : 
					begin //LOAD
					iadres = iadres + 1;
					regbrw = 1;
					end //LOAD

					`STORE :
					begin
					iadres = iadres + 1;
					drw = 1;
					end

					`JMP : 
					begin //JMP
					iadres = { 4'b0000, ir[`ARG0A:0] };
					end //JMP

					`JZ :  // use result from decode cycle
					begin //JZ
					if (regaval == 0) iadres = { 8'b00000000, ir[`ARG1A:0] };
					end //JZ
				
				endcase //(opcode)
			    end
			    
			 `LOADSTORE:
			    begin
			    exstate = `FETCH;
			    end
		endcase //(exstate)
       end //(clk) 
end // always

endmodule