// 
// DSP project. (c) Copyright 2003 Wayne Wolf
// Register file module

//clk: clock signal
//regaval: reg file out port 0
//regaadrs: reg file index add.
//regarw: read/write control sig.
//regawrite: reg file in port
module reg_file(clk,regaval,regaadrs,regarw,regawrite,regbval,regbadrs,regbrw,regbwrite);

	parameter n = 16; // instruction word width
	parameter nreg = 4; // number of registers 

	input clk;
	input [nreg-1:0] regaadrs, regbadrs;  // addresses for a, b
	output[n-1:0] regaval, regbval; // a, b data values
	input regarw, regbrw; // read/write for a, b
	input [n-1:0] regawrite, regbwrite; 

	reg[n-1:0] RegisterFile [0:nreg-1];  // the registers
	
	// read values
	assign regaval = RegisterFile[regaadrs];
	assign regbval = RegisterFile[regbadrs];
	
	always @(posedge clk)
	  begin
	    if(regarw) RegisterFile[regaadrs] = regawrite;
	    if(regbrw) RegisterFile[regbadrs] = regbwrite;
          end
endmodule