module ctrl(reset,clock,muxctrl1,muxctrl2,muxctrl3,muxctrl4,
		loadr1,loadr2,loadr3,loadr4);
    input reset, clock;
    output muxctrl1, muxctrl2, muxctrl4;
    output [1:0] muxctrl3;
    output loadr1, loadr2, loadr3, loadr4;
    reg muxctrl1, muxctrl2, muxctrl4, 
    	   loadr1, loadr2, loadr3, loadr4;
    reg [1:0] muxctrl3;

	reg [1:0] state;

	always @(posedge clock)
		begin
		if (reset == 1)
			begin
			muxctrl1 = 0; muxctrl2 = 0;
			muxctrl3 = 0; muxctrl4 = 0;
			loadr1 = 0; loadr2 = 0;
			loadr3 = 0; loadr4 = 0;
			state = 0;
			end
          else begin
			case (state)
				0: 
				begin
				muxctrl1 = 0; muxctrl2 = 0; 
				muxctrl3 = 0; muxctrl4 = 0;
				loadr1 = 1; loadr2 = 1; 
				loadr3 = 1; loadr4 = 1;
				state = 1;
				end
				1: 
				begin
				muxctrl1 = 1; muxctrl2 = 1; 
				muxctrl3 = 1; muxctrl4 = 1;
				loadr1 = 1; loadr2 = 1; 
				loadr3 = 0; loadr4 = 0;
				state = 2;
				end
				2: 
				begin
				muxctrl1 = 0; muxctrl2 = 0; 
				muxctrl3 = 2; muxctrl4 = 1;
				loadr1 = 0; loadr2 = 0; 
				loadr3 = 0; loadr4 = 0;
				state = 0;
				end
			endcase
		end // else
	end // always

endmodule