module dp(reset,clock,a,b,c,d,muxctrl1,muxctrl2,muxctrl3,
		muxctrl4,loadr1,loadr2,loadr3,loadr4,x3,z);
    parameter n=7;
    input reset;
    input clock;
    input [n:0] a, b, c, d; // data primary inputs
    input muxctrl1, muxctrl2, muxctrl4; // mux control
    input [1:0] muxctrl3; // 2-bit mux control
    input loadr1, loadr2, loadr3, loadr4; // register control
    output [n:0] x3, z;

	reg [n:0] r1, r2, r3, r4; // registers
	wire [n:0] mux1out, mux2out, mux3out, mux3bout, mux4out, 
			 mult1out, mult2out; 

	assign mux1out = (muxctrl1 == 0) ? a : r1;
	assign mux2out = (muxctrl2 == 0) ? b : r4;
	assign mux3out = (muxctrl3 == 0) ? a : (muxctrl3 == 1 ? r4 : r3);
	assign mux4out = (muxctrl4 == 0) ? c : r2;
	assign mult1out = mux1out * mux2out;
	assign mult2out = mux3out * mux4out;
	assign x3 = mult2out;
	assign z = mult1out;
	always @(posedge clock)
		begin
     	if (reset)
			begin
			r1 = 0; r2 = 0; r3 = 0; r4 = 0;
			end
		if (loadr1) r1 = mult1out;
		if (loadr2) r2 = mult2out;
		if (loadr3) r3 = c;
		if (loadr4) r4 = d;
		end
endmodule