module sys_testbench_v_tf();

// DATE:     10:44:24 12/29/2003 
// MODULE:   sys
// DESIGN:   sys
// FILENAME: testbench.v
// PROJECT:  ex6_2
// VERSION:  


// Inputs
    reg reset;
    reg clock;
    reg [7:0] a;
    reg [7:0] b;
    reg [7:0] c;
    reg [7:0] d;


// Outputs
    wire [7:0] x3;
    wire [7:0] z;


// Bidirs


// Instantiate the UUT
    sys uut (
        .reset(reset), 
        .clock(clock), 
        .a(a), 
        .b(b), 
        .c(c), 
        .d(d), 
        .x3(x3), 
        .z(z) 
        );


// Initialize Inputs
    `ifdef auto_init

        initial begin
            reset = 0;
            clock = 0;
            a = 0;
            b = 0;
            c = 0;
            d = 0;
        end

    `endif

	initial begin
	$monitor("a = %d, b = %d, c = %d, d = %d; x3 = %d, z = %d\n",
	    a,b,c,d,x3,z);
	#10 reset = 1; clock = 1;
	#10 clock = 0;
	#10 reset = 0; a = 1; b = 2; c = 3; d = 2; clock = 1;
	#10 clock = 0;
	#10 clock = 1;
	#10 clock = 0;
	#10 clock = 1;
	#10 clock = 0;
	#10 a = 1; b = 2; c = 1; d = 1; clock = 1;
	#10 clock = 0;
	#10 clock = 1;
	#10 clock = 0;
	#10 clock = 1;
	#10 clock = 0;
	#10 a = 2; b = 0; c = 2; d = 1; clock = 1;
	#10 clock = 0;
	#10 clock = 1;
	#10 clock = 0;
	#10 clock = 1;
	#10 clock = 0;
	#10 a = 3; b = 2; c = 4; d = 3; clock = 1;
	#10 clock = 0;
	#10 clock = 1;
	#10 clock = 0;
	#10 clock = 1;
	#10 clock = 0;
	$finish;
	end
endmodule