module nbitfulladd_testbench_v_tf();

// DATE:     16:15:06 12/20/2003 
// MODULE:   nbitfulladd
// DESIGN:   nbitfulladd
// FILENAME: testbench.v
// PROJECT:  nbitfulladd
// VERSION:  


// Inputs
    reg [7:0] a;
    reg [7:0] b;
    reg carryin;


// Outputs
    wire [7:0] sum;
    wire carryout;


// Bidirs


// Instantiate the UUT
    nbitfulladd uut (
        .a(a), 
        .b(b), 
        .carryin(carryin), 
        .sum(sum), 
        .carryout(carryout)
        );


// Initialize Inputs
    `ifdef auto_init

        initial begin
            a = 0;
            b = 0;
            carryin = 0;
        end

    `endif

	initial begin
	$monitor("a = %d, b = %d, cin = %d; sum = %d, cout = %d\n",
		a,b,carryin,sum,carryout);
     #10 a = 0; b = 0; carryin = 0;
     #10 a = 1; b = 0; carryin = 0;
     #10 a = 0; b = 0; carryin = 1;
     #10 a = 7; b = 5; carryin = 0;
     #10 a = 9; b = 3; carryin = 1;
     #10 a = 2; b = 27; carryin = 0;
     #10 a = 127; b = 0; carryin = 1;
     #10 a = 16; b = 128; carryin = 0;
     #10 a = 63; b = 222; carryin = 0;
     #10 a = 99; b = 129; carryin = 1;
     #10 a = 127; b = 127; carryin = 1;
     #10 a = 255; b = 255; carryin = 0;
     #10 a = 255; b = 255; carryin = 1;
	$finish;
	end

endmodule