module mod(rst,clock,i1,o1);
    parameter s0 = 0, s1 = 1;
    input rst;
    input clock;
    input i1;
    output o1;
    reg o1;

    reg [1:0] state;

always @(posedge clock) // start execution at the clock edge
begin
	if (rst == 1)
		begin
			// reset code
		end
	else begin // state machine
		case (state)
			s0: begin
				o1 = 0;
				state = s1;
				end
			s1: begin
				if (i1) o1 = 1; else o1 = 0;
				state = s0;
				end
		endcase
	end // state machine
end	// always


endmodule