module timer(rst,clk,long,short);
	input rst, clk; // reset and clock
	output long, short; // long and short timer outputs
	reg long, short; // hold output values

	reg [1:0] tval; // current state of timer

	always @(posedge clk) // update the timer and outputs
		begin
		if (rst == 1)
			begin
			tval = 0;
			short = 0;
			long = 0;
			end // reset
		else begin
			/* saturate counter until reset */
			tval = (tval == 3) ? tval : (tval + 1);
			long = (tval == 3) ? 1 : 0; // raise long at max
			short = (tval == 2) ? 1 : 0; // raise short at 2
			end // state machine
		end // always
endmodule