// Xilinx Verilog netlist produced by netgen application (version G.26)
// Command      : -sta -w tlc.ncd tlc_sta.v 
// Input file   : tlc.ncd
// Output file  : tlc_sta.v
// Design name  : tlc
// # of Modules : 1
// Xilinx       : C:/Xilinx
// Device       : 2v40cs144-4 (PRODUCTION 1.116 2003-11-04, STEPPING 1)

// This verilog netlist is a simulation model and uses library 
// primitives which may not represent the true implementation of 
// the device, however the netlist is functionally correct and 
// should not be modified. This file cannot be synthesized and 
// should only be used with supported static timing analysis tools. 

`timescale 1 ns/1 ps

module tlc (
  hy, hr, fy, fr, hg, fg, cars, rst, clk
);
  output hy;
  output hr;
  output fy;
  output fr;
  output hg;
  output fg;
  input cars;
  input rst;
  input clk;
  wire clk_BUFGP;
  wire rst_IBUF_0;
  wire s1__n0012;
  wire s1_state_FFd7_1;
  wire cars_IBUF_2;
  wire \clk_BUFGP/IBUFG_3 ;
  wire s1__n0014;
  wire s1__n0011;
  wire s1_state_FFd1_4;
  wire s1__n0010;
  wire GLOBAL_LOGIC1;
  wire \t1__n00011/O ;
  wire s1_count_reset_5;
  wire t1_long_6;
  wire \t1__n00001/O ;
  wire t1_short_7;
  wire \s1_state_FFd7-In_SW0/O ;
  wire \s1_state_FFd7-In/O ;
  wire s1_state_FFd3_8;
  wire \s1_state_FFd2-In ;
  wire s1_state_FFd2_9;
  wire s1__n0008;
  wire s1_state_FFd4_10;
  wire N1001;
  wire s1_state_FFd6_11;
  wire s1_state_FFd5_12;
  wire \s1_state_FFd4-In ;
  wire \s1_state_FFd6-In ;
  wire GLOBAL_LOGIC0;
  wire GLOBAL_LOGIC1_0;
  wire GLOBAL_LOGIC1_1;
  wire GLOBAL_LOGIC1_2;
  wire \fg/OUTPUT/OFF/O1INV_13 ;
  wire \fg/OUTPUT/OFF/OCEINVNOT ;
  wire s1_fg_14;
  wire \fg/OUTPUT/OTCLK1INV_15 ;
  wire \hg/OUTPUT/OTCLK1INV_16 ;
  wire s1_hg_17;
  wire \hg/OUTPUT/OFF/OCEINVNOT ;
  wire \hg/OUTPUT/OFF/O1INV_18 ;
  wire \cars/INBUF ;
  wire \clk/INBUF ;
  wire \rst/INBUF ;
  wire \clk_BUFGP/BUFG/S_INVNOT ;
  wire \t1_long/DYMUX_19 ;
  wire \t1_long/G ;
  wire \t1_long/SRFFMUX_20 ;
  wire \t1_long/CLKINV_21 ;
  wire \t1_short/DYMUX_22 ;
  wire \t1_short/G ;
  wire \t1_short/SRFFMUX_23 ;
  wire \t1_short/CLKINV_24 ;
  wire \s1_state_FFd7/DXMUX_25 ;
  wire \s1_state_FFd7/F ;
  wire \s1_state_FFd7/G ;
  wire \s1_state_FFd7/SRFFMUX_26 ;
  wire \s1_state_FFd7/CLKINV_27 ;
  wire \s1_state_FFd2/DXMUX_28 ;
  wire \s1_state_FFd2/F ;
  wire \s1_state_FFd2/DYMUX_29 ;
  wire \s1_state_FFd2/G ;
  wire \s1_state_FFd2/SRFFMUX_30 ;
  wire \s1_state_FFd2/CLKINV_31 ;
  wire \s1_state_FFd3/F ;
  wire \s1_state_FFd3/REVUSED_32 ;
  wire \s1_state_FFd3/DYMUX_33 ;
  wire \s1_state_FFd3/G ;
  wire \s1_state_FFd3/SRFFMUX_34 ;
  wire \s1_state_FFd3/CLKINV_35 ;
  wire \s1_state_FFd4/F ;
  wire \s1_state_FFd4/DYMUX_36 ;
  wire \s1_state_FFd4/G ;
  wire \s1_state_FFd4/SRFFMUX_37 ;
  wire \s1_state_FFd4/CLKINV_38 ;
  wire \s1_state_FFd6/F ;
  wire \s1_state_FFd6/DYMUX_39 ;
  wire \s1_state_FFd6/G ;
  wire \s1_state_FFd6/SRFFMUX_40 ;
  wire \s1_state_FFd6/CLKINV_41 ;
  wire \t1_tval<0>/DXMUX_42 ;
  wire \t1_tval<0>/BXINVNOT ;
  wire \t1_tval<0>/REVUSED_43 ;
  wire \t1_tval<0>/SRFFMUX_44 ;
  wire \t1_tval<0>/CLKINV_45 ;
  wire \t1_tval<1>/DXMUX_46 ;
  wire \t1_tval<1>/REVUSED_47 ;
  wire \t1_tval<1>/SRFFMUX_48 ;
  wire \t1_tval<1>/CLKINV_49 ;
  wire \s1__n0011/G ;
  wire \s1_state_FFd1/DXMUX_50 ;
  wire \s1_state_FFd1/BXINVNOT ;
  wire \s1_state_FFd1/REVUSED_51 ;
  wire \s1_state_FFd1/SRFFMUX_52 ;
  wire \s1_state_FFd1/CLKINV_53 ;
  wire \s1_state_FFd1/CEINV_54 ;
  wire \s1_state_FFd5/DXMUX_55 ;
  wire \s1_state_FFd5/BXINVNOT ;
  wire \s1_state_FFd5/REVUSED_56 ;
  wire \s1_state_FFd5/SRFFMUX_57 ;
  wire \s1_state_FFd5/CLKINV_58 ;
  wire \s1_state_FFd5/CEINV_59 ;
  wire \fr/OUTPUT/OTCLK1INV_60 ;
  wire s1_fr_61;
  wire \fr/OUTPUT/OFF/OCEINVNOT ;
  wire \fr/OUTPUT/OFF/O1INV_62 ;
  wire \hr/OUTPUT/OFF/O1INV_63 ;
  wire \hr/OUTPUT/OFF/OCEINVNOT ;
  wire s1_hr_64;
  wire \hr/OUTPUT/OTCLK1INV_65 ;
  wire \fy/OUTPUT/OFF/O1INV_66 ;
  wire \fy/OUTPUT/OFF/OCEINVNOT ;
  wire s1_fy_67;
  wire \fy/OUTPUT/OTCLK1INV_68 ;
  wire \hy/OUTPUT/OFF/O1INV_69 ;
  wire \hy/OUTPUT/OFF/OCEINVNOT ;
  wire s1_hy_70;
  wire \hy/OUTPUT/OTCLK1INV_71 ;
  wire GND;
  wire VCC;
  wire [1 : 0] t1_tval;
  X_ZERO \GLOBAL_LOGIC0.ZERO  (
    .O(GLOBAL_LOGIC0)
  );
  X_FF s1_fg (
    .I(\fg/OUTPUT/OFF/O1INV_13 ),
    .CE(\fg/OUTPUT/OFF/OCEINVNOT ),
    .CLK(\fg/OUTPUT/OTCLK1INV_15 ),
    .SET(GND),
    .RST(GND),
    .O(s1_fg_14)
  );
  X_BUF \fg/OUTPUT/OFF/O1INV  (
    .I(s1__n0012),
    .O(\fg/OUTPUT/OFF/O1INV_13 )
  );
  X_INV \fg/OUTPUT/OFF/OCEINV  (
    .I(rst_IBUF_0),
    .O(\fg/OUTPUT/OFF/OCEINVNOT )
  );
  X_BUF \fg/OUTPUT/OTCLK1INV  (
    .I(clk_BUFGP),
    .O(\fg/OUTPUT/OTCLK1INV_15 )
  );
  X_BUF fg_OBUF (
    .I(s1_fg_14),
    .O(fg)
  );
  X_BUF \hg/OUTPUT/OTCLK1INV  (
    .I(clk_BUFGP),
    .O(\hg/OUTPUT/OTCLK1INV_16 )
  );
  X_INV \hg/OUTPUT/OFF/OCEINV  (
    .I(rst_IBUF_0),
    .O(\hg/OUTPUT/OFF/OCEINVNOT )
  );
  X_BUF \hg/OUTPUT/OFF/O1INV  (
    .I(s1_state_FFd7_1),
    .O(\hg/OUTPUT/OFF/O1INV_18 )
  );
  X_BUF hg_OBUF (
    .I(s1_hg_17),
    .O(hg)
  );
  X_BUF cars_IBUF (
    .I(cars),
    .O(\cars/INBUF )
  );
  X_BUF \clk_BUFGP/IBUFG  (
    .I(clk),
    .O(\clk/INBUF )
  );
  X_BUF fr_OBUF (
    .I(s1_fr_61),
    .O(fr)
  );
  X_BUF hr_OBUF (
    .I(s1_hr_64),
    .O(hr)
  );
  X_BUF fy_OBUF (
    .I(s1_fy_67),
    .O(fy)
  );
  X_BUF hy_OBUF (
    .I(s1_hy_70),
    .O(hy)
  );
  X_BUF rst_IBUF (
    .I(rst),
    .O(\rst/INBUF )
  );
  X_BUFGMUX \clk_BUFGP/BUFG  (
    .I0(\clk_BUFGP/IBUFG_3 ),
    .I1(GND),
    .S(\clk_BUFGP/BUFG/S_INVNOT ),
    .O(clk_BUFGP)
  );
  X_INV \clk_BUFGP/BUFG/SINV  (
    .I(GLOBAL_LOGIC1),
    .O(\clk_BUFGP/BUFG/S_INVNOT )
  );
  X_BUF \t1_long/DYMUX  (
    .I(GLOBAL_LOGIC1_2),
    .O(\t1_long/DYMUX_19 )
  );
  X_BUF \t1_long/YUSED  (
    .I(\t1_long/G ),
    .O(\t1__n00011/O )
  );
  X_BUF \t1_long/SRFFMUX  (
    .I(\t1__n00011/O ),
    .O(\t1_long/SRFFMUX_20 )
  );
  X_BUF \t1_long/CLKINV  (
    .I(clk_BUFGP),
    .O(\t1_long/CLKINV_21 )
  );
  X_BUF \t1_short/DYMUX  (
    .I(GLOBAL_LOGIC1_1),
    .O(\t1_short/DYMUX_22 )
  );
  X_BUF \t1_short/YUSED  (
    .I(\t1_short/G ),
    .O(\t1__n00001/O )
  );
  X_BUF \t1_short/SRFFMUX  (
    .I(\t1__n00001/O ),
    .O(\t1_short/SRFFMUX_23 )
  );
  X_BUF \t1_short/CLKINV  (
    .I(clk_BUFGP),
    .O(\t1_short/CLKINV_24 )
  );
  X_BUF \s1_state_FFd7/DXMUX  (
    .I(\s1_state_FFd7-In/O ),
    .O(\s1_state_FFd7/DXMUX_25 )
  );
  X_BUF \s1_state_FFd7/XUSED  (
    .I(\s1_state_FFd7/F ),
    .O(\s1_state_FFd7-In/O )
  );
  X_BUF \s1_state_FFd7/YUSED  (
    .I(\s1_state_FFd7/G ),
    .O(\s1_state_FFd7-In_SW0/O )
  );
  X_BUF \s1_state_FFd7/SRFFMUX  (
    .I(rst_IBUF_0),
    .O(\s1_state_FFd7/SRFFMUX_26 )
  );
  X_BUF \s1_state_FFd7/CLKINV  (
    .I(clk_BUFGP),
    .O(\s1_state_FFd7/CLKINV_27 )
  );
  X_FF s1_hg (
    .I(\hg/OUTPUT/OFF/O1INV_18 ),
    .CE(\hg/OUTPUT/OFF/OCEINVNOT ),
    .CLK(\hg/OUTPUT/OTCLK1INV_16 ),
    .SET(GND),
    .RST(GND),
    .O(s1_hg_17)
  );
  X_BUF \s1_state_FFd2/DXMUX  (
    .I(\s1_state_FFd2-In ),
    .O(\s1_state_FFd2/DXMUX_28 )
  );
  X_BUF \s1_state_FFd2/XUSED  (
    .I(\s1_state_FFd2/F ),
    .O(\s1_state_FFd2-In )
  );
  X_BUF \s1_state_FFd2/DYMUX  (
    .I(s1__n0008),
    .O(\s1_state_FFd2/DYMUX_29 )
  );
  X_BUF \s1_state_FFd2/YUSED  (
    .I(\s1_state_FFd2/G ),
    .O(s1__n0008)
  );
  X_BUF \s1_state_FFd2/SRFFMUX  (
    .I(rst_IBUF_0),
    .O(\s1_state_FFd2/SRFFMUX_30 )
  );
  X_BUF \s1_state_FFd2/CLKINV  (
    .I(clk_BUFGP),
    .O(\s1_state_FFd2/CLKINV_31 )
  );
  X_BUF \s1_state_FFd3/XUSED  (
    .I(\s1_state_FFd3/F ),
    .O(s1__n0012)
  );
  X_BUF \s1_state_FFd3/REVUSED  (
    .I(s1_state_FFd4_10),
    .O(\s1_state_FFd3/REVUSED_32 )
  );
  X_BUF \s1_state_FFd3/DYMUX  (
    .I(N1001),
    .O(\s1_state_FFd3/DYMUX_33 )
  );
  X_BUF \s1_state_FFd3/YUSED  (
    .I(\s1_state_FFd3/G ),
    .O(N1001)
  );
  X_BUF \s1_state_FFd3/SRFFMUX  (
    .I(rst_IBUF_0),
    .O(\s1_state_FFd3/SRFFMUX_34 )
  );
  X_BUF \s1_state_FFd3/CLKINV  (
    .I(clk_BUFGP),
    .O(\s1_state_FFd3/CLKINV_35 )
  );
  X_BUF \s1_state_FFd4/XUSED  (
    .I(\s1_state_FFd4/F ),
    .O(s1__n0010)
  );
  X_BUF \s1_state_FFd4/DYMUX  (
    .I(\s1_state_FFd4-In ),
    .O(\s1_state_FFd4/DYMUX_36 )
  );
  X_BUF \s1_state_FFd4/YUSED  (
    .I(\s1_state_FFd4/G ),
    .O(\s1_state_FFd4-In )
  );
  X_BUF \s1_state_FFd4/SRFFMUX  (
    .I(rst_IBUF_0),
    .O(\s1_state_FFd4/SRFFMUX_37 )
  );
  X_BUF \s1_state_FFd4/CLKINV  (
    .I(clk_BUFGP),
    .O(\s1_state_FFd4/CLKINV_38 )
  );
  X_BUF \s1_state_FFd6/XUSED  (
    .I(\s1_state_FFd6/F ),
    .O(s1__n0014)
  );
  X_BUF \s1_state_FFd6/DYMUX  (
    .I(\s1_state_FFd6-In ),
    .O(\s1_state_FFd6/DYMUX_39 )
  );
  X_BUF \s1_state_FFd6/YUSED  (
    .I(\s1_state_FFd6/G ),
    .O(\s1_state_FFd6-In )
  );
  X_BUF \s1_state_FFd6/SRFFMUX  (
    .I(rst_IBUF_0),
    .O(\s1_state_FFd6/SRFFMUX_40 )
  );
  X_BUF \s1_state_FFd6/CLKINV  (
    .I(clk_BUFGP),
    .O(\s1_state_FFd6/CLKINV_41 )
  );
  X_BUF \t1_tval<0>/DXMUX  (
    .I(\t1_tval<0>/BXINVNOT ),
    .O(\t1_tval<0>/DXMUX_42 )
  );
  X_INV \t1_tval<0>/BXINV  (
    .I(t1_tval[0]),
    .O(\t1_tval<0>/BXINVNOT )
  );
  X_BUF \t1_tval<0>/REVUSED  (
    .I(t1_tval[1]),
    .O(\t1_tval<0>/REVUSED_43 )
  );
  X_BUF \t1_tval<0>/SRFFMUX  (
    .I(s1_count_reset_5),
    .O(\t1_tval<0>/SRFFMUX_44 )
  );
  X_BUF \t1_tval<0>/CLKINV  (
    .I(clk_BUFGP),
    .O(\t1_tval<0>/CLKINV_45 )
  );
  X_BUF \t1_tval<1>/DXMUX  (
    .I(t1_tval[1]),
    .O(\t1_tval<1>/DXMUX_46 )
  );
  X_BUF \t1_tval<1>/REVUSED  (
    .I(t1_tval[0]),
    .O(\t1_tval<1>/REVUSED_47 )
  );
  X_BUF \t1_tval<1>/SRFFMUX  (
    .I(s1_count_reset_5),
    .O(\t1_tval<1>/SRFFMUX_48 )
  );
  X_BUF \t1_tval<1>/CLKINV  (
    .I(clk_BUFGP),
    .O(\t1_tval<1>/CLKINV_49 )
  );
  X_BUF \s1__n0011/YUSED  (
    .I(\s1__n0011/G ),
    .O(s1__n0011)
  );
  X_BUF \s1_state_FFd1/DXMUX  (
    .I(\s1_state_FFd1/BXINVNOT ),
    .O(\s1_state_FFd1/DXMUX_50 )
  );
  X_INV \s1_state_FFd1/BXINV  (
    .I(GLOBAL_LOGIC1_0),
    .O(\s1_state_FFd1/BXINVNOT )
  );
  X_BUF \s1_state_FFd1/REVUSED  (
    .I(s1_state_FFd2_9),
    .O(\s1_state_FFd1/REVUSED_51 )
  );
  X_BUF \s1_state_FFd1/SRFFMUX  (
    .I(rst_IBUF_0),
    .O(\s1_state_FFd1/SRFFMUX_52 )
  );
  X_BUF \s1_state_FFd1/CLKINV  (
    .I(clk_BUFGP),
    .O(\s1_state_FFd1/CLKINV_53 )
  );
  X_BUF \s1_state_FFd1/CEINV  (
    .I(t1_short_7),
    .O(\s1_state_FFd1/CEINV_54 )
  );
  X_BUF \s1_state_FFd5/DXMUX  (
    .I(\s1_state_FFd5/BXINVNOT ),
    .O(\s1_state_FFd5/DXMUX_55 )
  );
  X_INV \s1_state_FFd5/BXINV  (
    .I(GLOBAL_LOGIC1_2),
    .O(\s1_state_FFd5/BXINVNOT )
  );
  X_BUF \s1_state_FFd5/REVUSED  (
    .I(s1_state_FFd6_11),
    .O(\s1_state_FFd5/REVUSED_56 )
  );
  X_BUF \s1_state_FFd5/SRFFMUX  (
    .I(rst_IBUF_0),
    .O(\s1_state_FFd5/SRFFMUX_57 )
  );
  X_BUF \s1_state_FFd5/CLKINV  (
    .I(clk_BUFGP),
    .O(\s1_state_FFd5/CLKINV_58 )
  );
  X_BUF \s1_state_FFd5/CEINV  (
    .I(t1_short_7),
    .O(\s1_state_FFd5/CEINV_59 )
  );
  X_BUF \fr/OUTPUT/OTCLK1INV  (
    .I(clk_BUFGP),
    .O(\fr/OUTPUT/OTCLK1INV_60 )
  );
  X_INV \fr/OUTPUT/OFF/OCEINV  (
    .I(rst_IBUF_0),
    .O(\fr/OUTPUT/OFF/OCEINVNOT )
  );
  X_BUF \fr/OUTPUT/OFF/O1INV  (
    .I(s1__n0014),
    .O(\fr/OUTPUT/OFF/O1INV_62 )
  );
  X_FF s1_fr (
    .I(\fr/OUTPUT/OFF/O1INV_62 ),
    .CE(\fr/OUTPUT/OFF/OCEINVNOT ),
    .CLK(\fr/OUTPUT/OTCLK1INV_60 ),
    .SET(GND),
    .RST(GND),
    .O(s1_fr_61)
  );
  X_BUF \hr/OUTPUT/OFF/O1INV  (
    .I(s1__n0011),
    .O(\hr/OUTPUT/OFF/O1INV_63 )
  );
  X_INV \hr/OUTPUT/OFF/OCEINV  (
    .I(rst_IBUF_0),
    .O(\hr/OUTPUT/OFF/OCEINVNOT )
  );
  X_BUF \hr/OUTPUT/OTCLK1INV  (
    .I(clk_BUFGP),
    .O(\hr/OUTPUT/OTCLK1INV_65 )
  );
  X_FF s1_hr (
    .I(\hr/OUTPUT/OFF/O1INV_63 ),
    .CE(\hr/OUTPUT/OFF/OCEINVNOT ),
    .CLK(\hr/OUTPUT/OTCLK1INV_65 ),
    .SET(GND),
    .RST(GND),
    .O(s1_hr_64)
  );
  X_BUF \fy/OUTPUT/OFF/O1INV  (
    .I(s1_state_FFd1_4),
    .O(\fy/OUTPUT/OFF/O1INV_66 )
  );
  X_INV \fy/OUTPUT/OFF/OCEINV  (
    .I(rst_IBUF_0),
    .O(\fy/OUTPUT/OFF/OCEINVNOT )
  );
  X_BUF \fy/OUTPUT/OTCLK1INV  (
    .I(clk_BUFGP),
    .O(\fy/OUTPUT/OTCLK1INV_68 )
  );
  X_FF s1_fy (
    .I(\fy/OUTPUT/OFF/O1INV_66 ),
    .CE(\fy/OUTPUT/OFF/OCEINVNOT ),
    .CLK(\fy/OUTPUT/OTCLK1INV_68 ),
    .SET(GND),
    .RST(GND),
    .O(s1_fy_67)
  );
  X_LUT4MUX16 \s1_state_FFd4-In1  (
    .I0(1'b0),
    .I1(1'b0),
    .I2(1'b0),
    .I3(1'b0),
    .I4(1'b0),
    .I5(1'b1),
    .I6(1'b0),
    .I7(1'b1),
    .I8(1'b0),
    .I9(1'b0),
    .I10(1'b0),
    .I11(1'b0),
    .I12(1'b0),
    .I13(1'b1),
    .I14(1'b0),
    .I15(1'b1),
    .ADR0(s1_state_FFd5_12),
    .ADR1(VCC),
    .ADR2(t1_short_7),
    .ADR3(VCC),
    .O(\s1_state_FFd4/G )
  );
  X_LUT4MUX16 \s1_state_FFd6-In1  (
    .I0(1'b0),
    .I1(1'b0),
    .I2(1'b0),
    .I3(1'b0),
    .I4(1'b0),
    .I5(1'b0),
    .I6(1'b0),
    .I7(1'b1),
    .I8(1'b0),
    .I9(1'b0),
    .I10(1'b0),
    .I11(1'b0),
    .I12(1'b0),
    .I13(1'b0),
    .I14(1'b0),
    .I15(1'b1),
    .ADR0(s1_state_FFd7_1),
    .ADR1(t1_long_6),
    .ADR2(cars_IBUF_2),
    .ADR3(VCC),
    .O(\s1_state_FFd6/G )
  );
  X_SFF s1_state_FFd4 (
    .I(\s1_state_FFd4/DYMUX_36 ),
    .CE(VCC),
    .CLK(\s1_state_FFd4/CLKINV_38 ),
    .SET(GND),
    .RST(GND),
    .SSET(GND),
    .SRST(\s1_state_FFd4/SRFFMUX_37 ),
    .O(s1_state_FFd4_10)
  );
  X_LUT4MUX16 s1__n00101 (
    .I0(1'b0),
    .I1(1'b1),
    .I2(1'b0),
    .I3(1'b1),
    .I4(1'b0),
    .I5(1'b1),
    .I6(1'b0),
    .I7(1'b1),
    .I8(1'b1),
    .I9(1'b1),
    .I10(1'b1),
    .I11(1'b1),
    .I12(1'b1),
    .I13(1'b1),
    .I14(1'b1),
    .I15(1'b1),
    .ADR0(s1_state_FFd5_12),
    .ADR1(VCC),
    .ADR2(VCC),
    .ADR3(s1_state_FFd6_11),
    .O(\s1_state_FFd4/F )
  );
  X_SFF s1_state_FFd6 (
    .I(\s1_state_FFd6/DYMUX_39 ),
    .CE(VCC),
    .CLK(\s1_state_FFd6/CLKINV_41 ),
    .SET(GND),
    .RST(GND),
    .SSET(GND),
    .SRST(\s1_state_FFd6/SRFFMUX_40 ),
    .O(s1_state_FFd6_11)
  );
  X_LUT4MUX16 s1__n00111 (
    .I0(1'b0),
    .I1(1'b1),
    .I2(1'b1),
    .I3(1'b1),
    .I4(1'b1),
    .I5(1'b1),
    .I6(1'b1),
    .I7(1'b1),
    .I8(1'b1),
    .I9(1'b1),
    .I10(1'b1),
    .I11(1'b1),
    .I12(1'b1),
    .I13(1'b1),
    .I14(1'b1),
    .I15(1'b1),
    .ADR0(s1_state_FFd2_9),
    .ADR1(s1_state_FFd3_8),
    .ADR2(s1_state_FFd4_10),
    .ADR3(s1_state_FFd1_4),
    .O(\s1__n0011/G )
  );
  X_LUT4MUX16 s1__n00141 (
    .I0(1'b0),
    .I1(1'b1),
    .I2(1'b0),
    .I3(1'b1),
    .I4(1'b1),
    .I5(1'b1),
    .I6(1'b1),
    .I7(1'b1),
    .I8(1'b1),
    .I9(1'b1),
    .I10(1'b1),
    .I11(1'b1),
    .I12(1'b1),
    .I13(1'b1),
    .I14(1'b1),
    .I15(1'b1),
    .ADR0(s1_state_FFd5_12),
    .ADR1(VCC),
    .ADR2(s1_state_FFd7_1),
    .ADR3(s1_state_FFd6_11),
    .O(\s1_state_FFd6/F )
  );
  X_SFF t1_tval_0 (
    .I(\t1_tval<0>/DXMUX_42 ),
    .CE(VCC),
    .CLK(\t1_tval<0>/CLKINV_45 ),
    .SET(GND),
    .RST(GND),
    .SSET(\t1_tval<0>/REVUSED_43 ),
    .SRST(\t1_tval<0>/SRFFMUX_44 ),
    .O(t1_tval[0])
  );
  X_LUT4MUX16 \s1_state_FFd7-In_SW0  (
    .I0(1'b0),
    .I1(1'b0),
    .I2(1'b0),
    .I3(1'b0),
    .I4(1'b0),
    .I5(1'b1),
    .I6(1'b0),
    .I7(1'b1),
    .I8(1'b0),
    .I9(1'b0),
    .I10(1'b0),
    .I11(1'b0),
    .I12(1'b0),
    .I13(1'b1),
    .I14(1'b0),
    .I15(1'b1),
    .ADR0(t1_short_7),
    .ADR1(VCC),
    .ADR2(s1_state_FFd1_4),
    .ADR3(VCC),
    .O(\s1_state_FFd7/G )
  );
  X_LUT4MUX16 \s1_state_FFd7-In  (
    .I0(1'b0),
    .I1(1'b0),
    .I2(1'b0),
    .I3(1'b0),
    .I4(1'b1),
    .I5(1'b1),
    .I6(1'b1),
    .I7(1'b1),
    .I8(1'b1),
    .I9(1'b1),
    .I10(1'b1),
    .I11(1'b0),
    .I12(1'b1),
    .I13(1'b1),
    .I14(1'b1),
    .I15(1'b1),
    .ADR0(cars_IBUF_2),
    .ADR1(t1_long_6),
    .ADR2(\s1_state_FFd7-In_SW0/O ),
    .ADR3(s1_state_FFd7_1),
    .O(\s1_state_FFd7/F )
  );
  X_LUT4MUX16 s1__n00081 (
    .I0(1'b0),
    .I1(1'b0),
    .I2(1'b0),
    .I3(1'b0),
    .I4(1'b1),
    .I5(1'b1),
    .I6(1'b1),
    .I7(1'b1),
    .I8(1'b0),
    .I9(1'b0),
    .I10(1'b0),
    .I11(1'b1),
    .I12(1'b0),
    .I13(1'b1),
    .I14(1'b0),
    .I15(1'b1),
    .ADR0(t1_long_6),
    .ADR1(s1_state_FFd7_1),
    .ADR2(s1_state_FFd3_8),
    .ADR3(cars_IBUF_2),
    .O(\s1_state_FFd2/G )
  );
  X_SFF s1_state_FFd7 (
    .I(\s1_state_FFd7/DXMUX_25 ),
    .CE(VCC),
    .CLK(\s1_state_FFd7/CLKINV_27 ),
    .SET(GND),
    .RST(GND),
    .SSET(\s1_state_FFd7/SRFFMUX_26 ),
    .SRST(GND),
    .O(s1_state_FFd7_1)
  );
  X_SFF s1_count_reset (
    .I(\s1_state_FFd2/DYMUX_29 ),
    .CE(VCC),
    .CLK(\s1_state_FFd2/CLKINV_31 ),
    .SET(GND),
    .RST(GND),
    .SSET(\s1_state_FFd2/SRFFMUX_30 ),
    .SRST(GND),
    .O(s1_count_reset_5)
  );
  X_LUT4MUX16 \s1_state_FFd2-In1  (
    .I0(1'b0),
    .I1(1'b0),
    .I2(1'b0),
    .I3(1'b0),
    .I4(1'b1),
    .I5(1'b1),
    .I6(1'b1),
    .I7(1'b1),
    .I8(1'b0),
    .I9(1'b0),
    .I10(1'b0),
    .I11(1'b0),
    .I12(1'b0),
    .I13(1'b1),
    .I14(1'b0),
    .I15(1'b1),
    .ADR0(t1_long_6),
    .ADR1(VCC),
    .ADR2(s1_state_FFd3_8),
    .ADR3(cars_IBUF_2),
    .O(\s1_state_FFd2/F )
  );
  X_LUT4MUX16 \s1_state_FFd3-In11  (
    .I0(1'b0),
    .I1(1'b0),
    .I2(1'b0),
    .I3(1'b0),
    .I4(1'b0),
    .I5(1'b0),
    .I6(1'b0),
    .I7(1'b0),
    .I8(1'b0),
    .I9(1'b0),
    .I10(1'b0),
    .I11(1'b0),
    .I12(1'b1),
    .I13(1'b0),
    .I14(1'b1),
    .I15(1'b0),
    .ADR0(t1_long_6),
    .ADR1(VCC),
    .ADR2(s1_state_FFd3_8),
    .ADR3(cars_IBUF_2),
    .O(\s1_state_FFd3/G )
  );
  X_SFF s1_state_FFd2 (
    .I(\s1_state_FFd2/DXMUX_28 ),
    .CE(VCC),
    .CLK(\s1_state_FFd2/CLKINV_31 ),
    .SET(GND),
    .RST(GND),
    .SSET(GND),
    .SRST(\s1_state_FFd2/SRFFMUX_30 ),
    .O(s1_state_FFd2_9)
  );
  X_SFF s1_state_FFd3 (
    .I(\s1_state_FFd3/DYMUX_33 ),
    .CE(VCC),
    .CLK(\s1_state_FFd3/CLKINV_35 ),
    .SET(GND),
    .RST(GND),
    .SSET(\s1_state_FFd3/REVUSED_32 ),
    .SRST(\s1_state_FFd3/SRFFMUX_34 ),
    .O(s1_state_FFd3_8)
  );
  X_LUT4MUX16 s1__n00121 (
    .I0(1'b0),
    .I1(1'b0),
    .I2(1'b1),
    .I3(1'b1),
    .I4(1'b1),
    .I5(1'b1),
    .I6(1'b1),
    .I7(1'b1),
    .I8(1'b1),
    .I9(1'b1),
    .I10(1'b1),
    .I11(1'b1),
    .I12(1'b1),
    .I13(1'b1),
    .I14(1'b1),
    .I15(1'b1),
    .ADR0(VCC),
    .ADR1(s1_state_FFd4_10),
    .ADR2(s1_state_FFd3_8),
    .ADR3(s1_state_FFd2_9),
    .O(\s1_state_FFd3/F )
  );
  X_BUF \hy/OUTPUT/OFF/O1INV  (
    .I(s1__n0010),
    .O(\hy/OUTPUT/OFF/O1INV_69 )
  );
  X_INV \hy/OUTPUT/OFF/OCEINV  (
    .I(rst_IBUF_0),
    .O(\hy/OUTPUT/OFF/OCEINVNOT )
  );
  X_BUF \hy/OUTPUT/OTCLK1INV  (
    .I(clk_BUFGP),
    .O(\hy/OUTPUT/OTCLK1INV_71 )
  );
  X_FF s1_hy (
    .I(\hy/OUTPUT/OFF/O1INV_69 ),
    .CE(\hy/OUTPUT/OFF/OCEINVNOT ),
    .CLK(\hy/OUTPUT/OTCLK1INV_71 ),
    .SET(GND),
    .RST(GND),
    .O(s1_hy_70)
  );
  X_LUT4MUX16 t1__n00011 (
    .I0(1'b1),
    .I1(1'b0),
    .I2(1'b1),
    .I3(1'b0),
    .I4(1'b1),
    .I5(1'b1),
    .I6(1'b1),
    .I7(1'b1),
    .I8(1'b1),
    .I9(1'b0),
    .I10(1'b1),
    .I11(1'b0),
    .I12(1'b1),
    .I13(1'b1),
    .I14(1'b1),
    .I15(1'b1),
    .ADR0(t1_tval[1]),
    .ADR1(VCC),
    .ADR2(s1_count_reset_5),
    .ADR3(VCC),
    .O(\t1_long/G )
  );
  X_SFF t1_long (
    .I(\t1_long/DYMUX_19 ),
    .CE(VCC),
    .CLK(\t1_long/CLKINV_21 ),
    .SET(GND),
    .RST(GND),
    .SSET(GND),
    .SRST(\t1_long/SRFFMUX_20 ),
    .O(t1_long_6)
  );
  X_LUT4MUX16 t1__n00001 (
    .I0(1'b1),
    .I1(1'b1),
    .I2(1'b1),
    .I3(1'b1),
    .I4(1'b1),
    .I5(1'b1),
    .I6(1'b1),
    .I7(1'b1),
    .I8(1'b0),
    .I9(1'b0),
    .I10(1'b1),
    .I11(1'b1),
    .I12(1'b1),
    .I13(1'b1),
    .I14(1'b1),
    .I15(1'b1),
    .ADR0(VCC),
    .ADR1(t1_tval[1]),
    .ADR2(s1_count_reset_5),
    .ADR3(t1_tval[0]),
    .O(\t1_short/G )
  );
  X_SFF t1_short (
    .I(\t1_short/DYMUX_22 ),
    .CE(VCC),
    .CLK(\t1_short/CLKINV_24 ),
    .SET(GND),
    .RST(GND),
    .SSET(GND),
    .SRST(\t1_short/SRFFMUX_23 ),
    .O(t1_short_7)
  );
  X_SFF t1_tval_1 (
    .I(\t1_tval<1>/DXMUX_46 ),
    .CE(VCC),
    .CLK(\t1_tval<1>/CLKINV_49 ),
    .SET(GND),
    .RST(GND),
    .SSET(\t1_tval<1>/REVUSED_47 ),
    .SRST(\t1_tval<1>/SRFFMUX_48 ),
    .O(t1_tval[1])
  );
  X_SFF s1_state_FFd1 (
    .I(\s1_state_FFd1/DXMUX_50 ),
    .CE(\s1_state_FFd1/CEINV_54 ),
    .CLK(\s1_state_FFd1/CLKINV_53 ),
    .SET(GND),
    .RST(GND),
    .SSET(\s1_state_FFd1/REVUSED_51 ),
    .SRST(\s1_state_FFd1/SRFFMUX_52 ),
    .O(s1_state_FFd1_4)
  );
  X_SFF s1_state_FFd5 (
    .I(\s1_state_FFd5/DXMUX_55 ),
    .CE(\s1_state_FFd5/CEINV_59 ),
    .CLK(\s1_state_FFd5/CLKINV_58 ),
    .SET(GND),
    .RST(GND),
    .SSET(\s1_state_FFd5/REVUSED_56 ),
    .SRST(\s1_state_FFd5/SRFFMUX_57 ),
    .O(s1_state_FFd5_12)
  );
  X_ONE \PWR_VCC_0/LOGICAL_ONE  (
    .O(GLOBAL_LOGIC1)
  );
  X_ONE \PWR_VCC_1/LOGICAL_ONE  (
    .O(GLOBAL_LOGIC1_0)
  );
  X_ONE \PWR_VCC_2/LOGICAL_ONE  (
    .O(GLOBAL_LOGIC1_1)
  );
  X_ONE \PWR_VCC_3/LOGICAL_ONE  (
    .O(GLOBAL_LOGIC1_2)
  );
  X_BUF \cars/IFF/IMUX  (
    .I(\cars/INBUF ),
    .O(cars_IBUF_2)
  );
  X_BUF \clk/IFF/IMUX  (
    .I(\clk/INBUF ),
    .O(\clk_BUFGP/IBUFG_3 )
  );
  X_BUF \rst/IFF/IMUX  (
    .I(\rst/INBUF ),
    .O(rst_IBUF_0)
  );
  X_ZERO NlwBlock_tlc_GND (
    .O(GND)
  );
  X_ONE NlwBlock_tlc_VCC (
    .O(VCC)
  );
endmodule