module tlc_tlc_testbench_v_tf();

// DATE:     23:18:41 11/10/2003 
// MODULE:   tlc
// DESIGN:   tlc
// FILENAME: tlc_testbench.v
// PROJECT:  tlc
// VERSION:  


// Inputs
    reg rst;
    reg clk;
    reg cars;


// Outputs
    wire hg;
    wire hy;
    wire hr;
    wire fg;
    wire fy;
    wire fr;


// Bidirs


// Instantiate the UUT
    tlc uut (
        .rst(rst), 
        .clk(clk), 
        .cars(cars), 
        .hg(hg), 
        .hy(hy), 
        .hr(hr), 
        .fg(fg), 
        .fy(fy), 
        .fr(fr)
        );


// Initialize Inputs
    `ifdef auto_init

        initial begin
            rst = 0;
            clk = 0;
            cars = 0;
        end

    `endif

	initial begin
	$monitor("clk = %d: cars = %d, hg = %d, hy = %d, hr = %d, fg = %d, fy = %d, fr = %d\n",
		clk,cars,hg,hy,hr,fg,fy,fr);
     #10 rst = 1; clk = 1; cars = 0;
	#10 clk = 0;
	#10 rst = 0; clk = 1;
	#10 clk = 0;
	#10 clk = 1; 
	#10 clk = 0;
  	#10 clk = 1; cars = 1; 
	#10 clk = 0;
	#10 clk = 1; cars = 1; 
	#10 clk = 0;
	#10 clk = 1; cars = 0; 
	#10 clk = 0;
 	#10 clk = 1; cars = 1; 
	#10 clk = 0;
 	#10 clk = 1; cars = 1; 
	#10 clk = 0;
 	#10 clk = 1; cars = 1; 
	#10 clk = 0;
 	#10 clk = 1; cars = 1; 
	#10 clk = 0;
 	#10 clk = 1; cars = 1; 
	#10 clk = 0;
 	#10 clk = 1; cars = 1; 
	#10 clk = 0;
 	#10 clk = 1; cars = 1; 
	#10 clk = 0;
 	#10 clk = 1; cars = 1; 
	#10 clk = 0;
 	#10 clk = 1; cars = 1; 
	#10 clk = 0;
 	#10 clk = 1; cars = 1; 
	#10 clk = 0;
 	#10 clk = 1; cars = 1; 
	#10 clk = 0;
 	#10 clk = 1; cars = 0; 
	#10 clk = 0;
 	#10 clk = 1; cars = 0; 
	#10 clk = 0;
 	#10 clk = 1; cars = 0; 
	#10 clk = 0;
 	#10 clk = 1; cars = 0; 
	#10 clk = 0;
 	#10 clk = 1; cars = 0; 
	#10 clk = 0;
 	#10 clk = 1; cars = 1; 
	#10 clk = 0;
 	#10 clk = 1; cars = 1; 
	#10 clk = 0;
 	#10 clk = 1; cars = 0; 
	#10 clk = 0;
 	#10 clk = 1; cars = 0; 
	#10 clk = 0;
 	#10 clk = 1; cars = 0; 
	#10 clk = 0;
 	#10 clk = 1; cars = 0; 
	#10 clk = 0;
 	#10 clk = 1; cars = 0; 
	#10 clk = 0;
 	#10 clk = 1; cars = 0; 
	#10 clk = 0;
 	#10 clk = 1; cars = 0; 
	#10 clk = 0;
	$finish;
	end

endmodule