module timer(rst,clk,long,short);
	input rst, clk; // reset and clock
	output long, short; // long and short timer outputs

	reg [3:0] tval; // current state of the timer

	always @(posedge clk) // update the timer and outputs
		if (rst == 1)
			begin
			tval = 4'b0000;
			short = 0;
			long = 0;
			end // reset
		else begin
			{long,tval} = tval + 1; // raise long at rollover
			if (tval == 4'b0100)
				short = 1'b1; // raise short after 2^2
		end // state machine
endmodule