Verilog and VHDL from the chapters (zip file of everything):

• ALU: alu.v, alu.prj, testbench.v
• array multiplier: array_mult.prj, array_mult.v, array_mult_vhdl.prj, coregen.prj, fulladd.prj, fulladd.v, fulladd_vhdl.prj, lastrow,prj, lastrow.v, lastrow_vhdl.prj, multcell.prj, multcell.v, multcell_vhdl.prj, multrow.v, multrow_vhdl.prj, testbench.v
• carry-skip adder: carryskip.prj, carryskip.v, carryskip_vhdl.prj, fulladd.v, fulladd_p.prj, fulladd_p_vhdl.prj, nbitfulladd.v, testbench.v
• carry lookahead adder: carry_block.prj, carry_block.v, carry_block_vhdl.prj, carry_lookahead.v, carry_lookahead_adder.prj, carry_lookahead_adder_vhdl.prj, cla.prj, cla_vhdl.prj, coregen.prj, fulladd.v, testbench.v
• DSP: alu.v, dsp.prj, dsp.v, dsp_vhdl.prj, ex.prj, ex.v, ex_vhdl.prj, reg.v
• Example 6-2: ctrl.v, ctrl_vhdl.prj, dp.prj, dp.v, dp_vhdl.prj, mult.prj, mult.v, mult_vhdl.prj, sys.prj, sys.v, sys_vhdl.prj, testbench.v
• traffic light controller: coregen.prj, sequencer_vhdl.prj, timer.prj, timer_vhdl.prj, tlc.prj, tlc.v, tlc_ctrl.v, tlc_sta.v, tlc_testbench.v, tlc_timer.v, tlc_vhdl.prj
• parity: coregen.prj, parity.prj, parity.v, parity_vhdl.prj, testbench.v
• n-bit full adder: coregen.prj, fulladd.prj, fulladd.v, fulladd_vhdl.prj, nbitfulladd.prj, nbitfulladd.v, nbitfulladd_vhdl.prj, testbench.v
• shifter: coregen.prj, shifter.prj, shifter.v, shifter_vhdl.prj, testbench.v
• Section 5.3.3 design: mod.prj, mod.v

Errata:

p. 103: Q2-8c. Use C = 0.9 fF/micron^2 (= 2.9 fF/unit square for a minimum-width wire), r = 4 Ohms/square.

p. 127, Example 3-6: A download cable can't be used in master serial mode.

p. 130: Q2-11. "minimum-resistance metal 1 wire" -> "minimum-width metal 1 wire"

p. 130: The truth table in Figure 3-11 is incorrect. Here is a (hopefully) correct truth table: